1. Field of the Invention
The present invention is related to a gated clock design technique by the use of a computer, and more particularly related to a computer aided design system for clock gated logic circuits, a computer-readable medium for storing the program of the system and a gated clock circuit.
2. Prior Art
In recent years, the frequencies of the clock signal for driving LSIs have been dramatically increased to require much power consumption.
The gated clock design technique has been developed for the purpose of obtaining logic circuit designs with low electric power consumption. The procedure of modifying logic circuits by means of the gated clock design technique is called “clock gating” in the following explanation.
FIG. 1(a) is a circuit diagram showing a clocked logic circuit with a clock tree structure that has not been clock gated. In the following example, registers to be controlled under the same register transfer condition (the same enable logic) are grouped into a set which is called a “cluster” in the following explanation. Also, in this example, there are ten register transfer conditions. Each register is subject to one of the register transfer conditions and belongs to a corresponding one of the ten clusters C0 to C9.
Since the circuit as illustrated in FIG. 1(a) is not designed in the clock gating structure, the clock signal CLK is supplied to all the clusters through the clock tree structure T in which the load is distributed uniformly. It is possible therefore to minimize the clock skew and therefore to finish the designing and developing process of an error free circuit in a short time within the schedule.
However, in recent years, since the frequency of the clock signal CLK has been dramatically increased to require so much power consumption that the increase of the electric power consumption becomes problematic in the case of the logic circuit as illustrated in FIG. 1(a). Furthermore, as illustrated in FIG. 1(b), which is a circuit diagram showing one register circuit for use in the clock tree structure of the clocked logic circuit that has not been clock gated, a feedback loop including a multiplexer 22 has to be provided for each register circuit in order to keep the current value in the register 21 when the register transfer condition is not satisfied. In this case, since the clock signal CLK is supplied always to all the register circuits to drive the entirety of the clock tree structure, the electric power consumption becomes significantly increased.
Because of this, such a circuit as described above is quite inappropriate to be applied to electric appliances powered by batteries such as mobile gears which are driven for short times after charging. It is therefore required to reduce the electric power consumption of the circuit.
In usual cases, it is believed effective to reduce the electric power consumption of the clock supply system for the purpose of reducing the electric power consumption of an LSI chip. The clock gating technique has been known as a most effective technique to reduce the electric power consumption of the clock supply system.
FIG. 2(a) is a circuit diagram showing an exemplary configuration of the clock tree structure of a gated clock logic circuit in accordance with a conventional technique. Register circuits belong to ten clusters and then belong respectively to ten partial trees T0 to T9, to which a clock signal CLK is supplied through AND gate circuits G0 to G9 provided for clock gating The clock signal CLK is supplied to the AND gate circuits G0 to G9 through a buffer circuit 1.
For example, since the register transfer condition En(C6) is input to one input terminal of the AND gate circuit G6, the clock signal CLK is supplied to the partial tree T6 when this register transfer condition (i.e. En(C6)=1) is satisfied while the clock signal CLK is not supplied to the partial tree T6 when this register transfer condition is not satisfied (i.e. En(C6)=0).
In this case, since there are 611 register circuits belonging to the cluster C6 to which the clock signal CLK is supplied only when the register transfer condition is satisfied, it is possible to keep the current value in the register 21 when the register transfer condition is not satisfied even if no feedback loop is provided for the register circuit 2 as illustrated in FIG. 2(b) resulting in a simplified circuit design.
Namely, in the case of the gated clock logic circuit in accordance with the conventional technique as illustrated in FIG. 2(a), since clock signal CLK is supplied to the register circuits only when the register transfer condition is satisfied, there is no need for the feedback loops to keep the current values in the registers, as illustrated in FIG. 1(b) when the register transfer condition is not satisfied so as to reduce the unnecessary clock pluses of supplying the clock signal to the register circuits, the unnecessary clock pluses of driving the clock tree structure and therefore the electric power consumption thereof.
However, the clock tree structure is composed of the combination of the partial trees for the respective clusters which have different numbers of the register circuits belonging thereto. For example, the differential number between the constituent register circuits of the partial tree T0 and the partial tree T6 is significant, i.e., 572, and therefore it is difficult to keep the clock skew within a tolerable range. As a result, when the skew is substantial, there is a problem of that the risk of device malfunctions is increased to require the designer to begin his work again so as to elongate the designing and development time.